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| author | Alistair Francis <alistair.francis@wdc.com> | 2019-10-08 16:32:07 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-10-28 07:47:27 -0700 |
| commit | a6902ef0e3a83ea3dcf54f1919d485d4cf148506 (patch) | |
| tree | 364617a96147f56626c4b2f1c0e178909f6cf8d6 /include/hw/riscv | |
| parent | 2921343b3df93e4848034ec615c01ee221212c3a (diff) | |
| download | qemu-a6902ef0e3a83ea3dcf54f1919d485d4cf148506.zip qemu-a6902ef0e3a83ea3dcf54f1919d485d4cf148506.tar.gz qemu-a6902ef0e3a83ea3dcf54f1919d485d4cf148506.tar.bz2 | |
riscv/sifive_u: Add L2-LIM cache memory
On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L2 LIM (LooselyIntegrated Memory).
Ideally we would want to adjust the size of this chunk of memory as the
L2 Cache Controller WayEnable register is incremented. Unfortunately I
don't see a nice way to handle reducing or blocking out the L2 LIM while
still allowing it be re returned to all enabled from a reset.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4850805..66ee76a 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -58,6 +58,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, SIFIVE_U_UART0, |