From a6902ef0e3a83ea3dcf54f1919d485d4cf148506 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 8 Oct 2019 16:32:07 -0700 Subject: riscv/sifive_u: Add L2-LIM cache memory On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the L2 LIM (LooselyIntegrated Memory). Ideally we would want to adjust the size of this chunk of memory as the L2 Cache Controller WayEnable register is incremented. Unfortunately I don't see a nice way to handle reducing or blocking out the L2 LIM while still allowing it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/riscv') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4850805..66ee76a 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -58,6 +58,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, SIFIVE_U_UART0, -- cgit v1.1