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author | Chalapathi V <chalapathi.v@linux.ibm.com> | 2024-01-23 16:37:02 +1000 |
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committer | Nicholas Piggin <npiggin@gmail.com> | 2024-02-23 23:24:42 +1000 |
commit | 5706b0064d6a78c32bf46f18910bc4e10dde2687 (patch) | |
tree | 4a05fad717b2c03dcc41ef3289cee26e182e8d46 /include/hw/ppc/pnv_n1_chiplet.h | |
parent | 1adf24708bf7f8506fab6f2d53530af0210e6658 (diff) | |
download | qemu-5706b0064d6a78c32bf46f18910bc4e10dde2687.zip qemu-5706b0064d6a78c32bf46f18910bc4e10dde2687.tar.gz qemu-5706b0064d6a78c32bf46f18910bc4e10dde2687.tar.bz2 |
hw/ppc: Add N1 chiplet model
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include/hw/ppc/pnv_n1_chiplet.h')
-rw-r--r-- | include/hw/ppc/pnv_n1_chiplet.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_n1_chiplet.h b/include/hw/ppc/pnv_n1_chiplet.h new file mode 100644 index 0000000..a7ad039 --- /dev/null +++ b/include/hw/ppc/pnv_n1_chiplet.h @@ -0,0 +1,32 @@ +/* + * QEMU PowerPC N1 chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_PNV_N1_CHIPLET_H +#define PPC_PNV_N1_CHIPLET_H + +#include "hw/ppc/pnv_nest_pervasive.h" + +#define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet" +#define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj), TYPE_PNV_N1_CHIPLET) + +typedef struct PnvPbScom { + uint64_t mode; + uint64_t hp_mode2_curr; +} PnvPbScom; + +typedef struct PnvN1Chiplet { + DeviceState parent; + MemoryRegion xscom_pb_eq_mr; + MemoryRegion xscom_pb_es_mr; + PnvNestChipletPervasive nest_pervasive; /* common pervasive chiplet unit */ +#define PNV_PB_SCOM_EQ_SIZE 8 + PnvPbScom eq[PNV_PB_SCOM_EQ_SIZE]; +#define PNV_PB_SCOM_ES_SIZE 4 + PnvPbScom es[PNV_PB_SCOM_ES_SIZE]; +} PnvN1Chiplet; +#endif /*PPC_PNV_N1_CHIPLET_H */ |