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| author | Tomasz Jeznach <tjeznach@rivosinc.com> | 2024-10-16 17:40:27 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-31 13:51:24 +1000 |
| commit | 0c54acb8243dfc51a021d108ffef794c89c84f72 (patch) | |
| tree | 999e950629f63ea7b925376dd1d30cac2980b26c /include/hw/pci | |
| parent | e21b3b243f75afd8b0986a40e5ef8107868d84e3 (diff) | |
| download | qemu-0c54acb8243dfc51a021d108ffef794c89c84f72.zip qemu-0c54acb8243dfc51a021d108ffef794c89c84f72.tar.gz qemu-0c54acb8243dfc51a021d108ffef794c89c84f72.tar.bz2 | |
hw/riscv: add RISC-V IOMMU base emulation
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V IOMMU. It includes
support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4,
sv39x4, sv48x4, sv57x4 caps).
Other capabilities like ATS and DBG support will be added incrementally
in the next patches.
Co-developed-by: Sebastien Boeuf <seb@rivosinc.com>
Signed-off-by: Sebastien Boeuf <seb@rivosinc.com>
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
Message-ID: <20241016204038.649340-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/pci')
0 files changed, 0 insertions, 0 deletions