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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-11-04 09:38:39 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-11-07 08:19:39 +1000 |
| commit | d3b96a53190dc52d436c39b03fb7533fef044869 (patch) | |
| tree | 9b4f9b7bada9646acdbdaa2ad48b3e629c888df9 /include/hw/misc/stm32l4x5_exti.h | |
| parent | cd5d265f42fbb1d29cbc9d8805821149101c1d23 (diff) | |
| download | qemu-d3b96a53190dc52d436c39b03fb7533fef044869.zip qemu-d3b96a53190dc52d436c39b03fb7533fef044869.tar.gz qemu-d3b96a53190dc52d436c39b03fb7533fef044869.tar.bz2 | |
hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check
'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.
'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.
Reported by Coverity via a "DEADCODE" ticket.
Resolves: Coverity CID 1564781
Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/misc/stm32l4x5_exti.h')
0 files changed, 0 insertions, 0 deletions