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| author | Samuel Tardieu <sam@rfc1149.net> | 2024-01-06 19:15:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:42:40 +0000 |
| commit | d09923ad19fc3d653693ee81f1742fb8d29c5730 (patch) | |
| tree | 13744d2cfb0219ca45f4a4232a112df876a4ac41 /include/hw/misc/stm32l4x5_exti.h | |
| parent | 41581f13619d0d66593a75c5299c8d546710cc9e (diff) | |
| download | qemu-d09923ad19fc3d653693ee81f1742fb8d29c5730.zip qemu-d09923ad19fc3d653693ee81f1742fb8d29c5730.tar.gz qemu-d09923ad19fc3d653693ee81f1742fb8d29c5730.tar.bz2 | |
hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240106181503.1746200-2-sam@rfc1149.net
Suggested-by: Anton Kochkov <anton.kochkov@proton.me>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/stm32l4x5_exti.h')
0 files changed, 0 insertions, 0 deletions