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authorJamin Lin <jamin_lin@aspeedtech.com>2024-07-04 16:29:18 +0800
committerCédric Le Goater <clg@redhat.com>2024-07-09 08:05:44 +0200
commit2095468d2cce73d1d3825cb953bd5114fffe73c8 (patch)
tree35086cde975fe100c6768fae7a7a487d2ba37915 /include/hw/misc/stm32l4x5_exti.h
parent578c6e9ed5d0484da5b478f932c420ecc4f751f6 (diff)
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hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. It have "TXDES 2" and "RXDES 2" to save the high part physical address of packet buffer. Ex: TX packet buffer address [34:0] The "TXDES 2" bits [18:16] which corresponds the bits [34:32] of the 64 bits address of the TX packet buffer address and "TXDES 3" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the TX packet buffer address. Update TX and RX packet buffers address type to 64 bits for dram 64 bits address DMA support. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include/hw/misc/stm32l4x5_exti.h')
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