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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-11-01 16:33:27 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-05 23:32:25 +0000 |
| commit | 07995a46bae9d2ec0971b435834c60a4df84b03f (patch) | |
| tree | 56b2a09a4cd529a8f342e0c64e9501e96a6ce23f /include/hw/misc/stm32l4x5_exti.h | |
| parent | f35c0221fef864e65db7641bb041c5f913e31475 (diff) | |
| download | qemu-07995a46bae9d2ec0971b435834c60a4df84b03f.zip qemu-07995a46bae9d2ec0971b435834c60a4df84b03f.tar.gz qemu-07995a46bae9d2ec0971b435834c60a4df84b03f.tar.bz2 | |
hw/core: Add a helper to check the cache topology level
Currently, we have no way to expose the arch-specific default cache
model because the cache model is sometimes related to the CPU model
(e.g., i386).
Since the user might configure "default" level, any comparison with
"default" is meaningless before the machine knows the specific level
that "default" refers to.
We can only check the correctness of the cache topology after the arch
loads the user-configured cache model from MachineState.smp_cache and
consumes the special "default" level by replacing it with the specific
level.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-6-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include/hw/misc/stm32l4x5_exti.h')
0 files changed, 0 insertions, 0 deletions