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| author | Hao Wu <wuhaotsh@google.com> | 2025-02-19 10:45:55 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 15:22:19 +0000 |
| commit | 506af2330cd0ef684a48aad12640a7bea8e95247 (patch) | |
| tree | ae112c9d1abe8a76a7dad78d4ccb91d6bc9e42d3 /include/hw/misc/npcm_gcr.h | |
| parent | e9be8467b42f7e2af70694422f4b4d8afe82bf4e (diff) | |
| download | qemu-506af2330cd0ef684a48aad12640a7bea8e95247.zip qemu-506af2330cd0ef684a48aad12640a7bea8e95247.tar.gz qemu-506af2330cd0ef684a48aad12640a7bea8e95247.tar.bz2 | |
hw/misc: Rename npcm7xx_gcr to npcm_gcr
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-5-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/npcm_gcr.h')
| -rw-r--r-- | include/hw/misc/npcm_gcr.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h new file mode 100644 index 0000000..9b49989 --- /dev/null +++ b/include/hw/misc/npcm_gcr.h @@ -0,0 +1,73 @@ +/* + * Nuvoton NPCM7xx System Global Control Registers. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM_GCR_H +#define NPCM_GCR_H + +#include "exec/memory.h" +#include "hw/sysbus.h" + +/* + * NPCM7XX PWRON STRAP bit fields + * 12: SPI0 powered by VSBV3 at 1.8V + * 11: System flash attached to BMC + * 10: BSP alternative pins. + * 9:8: Flash UART command route enabled. + * 7: Security enabled. + * 6: HI-Z state control. + * 5: ECC disabled. + * 4: Reserved + * 3: JTAG2 enabled. + * 2:0: CPU and DRAM clock frequency. + */ +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) +#define FUP_NORM_UART2 3 +#define FUP_PROG_UART3 2 +#define FUP_PROG_UART2 1 +#define FUP_NORM_UART3 0 +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) +#define CKFRQ_SKIPINIT 0x000 +#define CKFRQ_DEFAULT 0x111 + +/* + * Number of registers in our device state structure. Don't change this without + * incrementing the version_id in the vmstate. + */ +#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) + +struct NPCM7xxGCRState { + SysBusDevice parent; + + MemoryRegion iomem; + + uint32_t regs[NPCM7XX_GCR_NR_REGS]; + + uint32_t reset_pwron; + uint32_t reset_mdlr; + uint32_t reset_intcr3; +}; + +#define TYPE_NPCM7XX_GCR "npcm7xx-gcr" +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) + +#endif /* NPCM_GCR_H */ |