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| author | Hao Wu <wuhaotsh@google.com> | 2025-02-19 10:46:04 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 15:22:22 +0000 |
| commit | 4e67d50deaf3132f392266e7251cf7ce17be8fa4 (patch) | |
| tree | e19bbea97d70a9d497aa16b1dd7faaaf24e34739 /include/hw/misc/npcm_clk.h | |
| parent | cf76c4e174e128397763c4ec98b0aa3345bab3be (diff) | |
| download | qemu-4e67d50deaf3132f392266e7251cf7ce17be8fa4.zip qemu-4e67d50deaf3132f392266e7251cf7ce17be8fa4.tar.gz qemu-4e67d50deaf3132f392266e7251cf7ce17be8fa4.tar.bz2 | |
hw/misc: Support NPCM8XX CLK Module Registers
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-14-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/npcm_clk.h')
| -rw-r--r-- | include/hw/misc/npcm_clk.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index f47614a..8fa1e14 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -21,11 +21,12 @@ #include "hw/sysbus.h" #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) +#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t)) /* * Number of maximum registers in NPCM device state structure. Don't change * this without incrementing the version_id in the vmstate. */ -#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS +#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" @@ -162,6 +163,10 @@ struct NPCMCLKState { MemoryRegion iomem; /* Clock converters */ + /* + * TODO: Implement unique clock converters for NPCM8xx. + * NPCM8xx adds a few more clock outputs. + */ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; @@ -185,5 +190,6 @@ typedef struct NPCMCLKClass { #define TYPE_NPCM_CLK "npcm-clk" OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" +#define TYPE_NPCM8XX_CLK "npcm8xx-clk" #endif /* NPCM_CLK_H */ |