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| author | Arnaud Minier <arnaud.minier@telecom-paris.fr> | 2024-03-03 15:06:40 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:56 +0000 |
| commit | 9c796d503f9d2ee2f6948964d972a7ef23b62033 (patch) | |
| tree | 8e13b6c9227e2030a9bc84d5994bcab3e76b30ac /include/hw/mem/sparse-mem.h | |
| parent | 141c29a23bb8eb63c04199a2c3653195ca14f76a (diff) | |
| download | qemu-9c796d503f9d2ee2f6948964d972a7ef23b62033.zip qemu-9c796d503f9d2ee2f6948964d972a7ef23b62033.tar.gz qemu-9c796d503f9d2ee2f6948964d972a7ef23b62033.tar.bz2 | |
hw/misc/stm32l4x5_rcc: Handle Register Updates
Update the RCC state and propagate frequency changes when writing to the
RCC registers. Currently, ICSCR, CIER, the reset registers and the stop
mode registers are not implemented.
Some fields have not been implemented due to uncertainty about
how to handle them (Like the clock security system or bypassing
mecanisms).
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240303140643.81957-6-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/mem/sparse-mem.h')
0 files changed, 0 insertions, 0 deletions