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| author | David Woodhouse <dwmw2@infradead.org> | 2023-03-02 10:06:26 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-03-08 00:37:48 +0100 |
| commit | ecb0e98b4f24495dd4febab7d69579d62773bdc4 (patch) | |
| tree | 26d5b56defe053ab32f89e7ec80c2e06f6d5f1cc /include/hw/isa | |
| parent | 4e0210525752511646c737f89ea2f2e7c7ca85de (diff) | |
| download | qemu-ecb0e98b4f24495dd4febab7d69579d62773bdc4.zip qemu-ecb0e98b4f24495dd4febab7d69579d62773bdc4.tar.gz qemu-ecb0e98b4f24495dd4febab7d69579d62773bdc4.tar.bz2 | |
hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is
disabled', but apparently MorphOS is using it in the version of the
i8259 which is in the Pegasos2 board as part of the VT8231 chipset.
It's easy enough to implement, and I think it's harmless enough to do so
unconditionally.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
[balaton: updated commit message as asked by author]
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <3f09b2dd109d19851d786047ad5c2ff459c90cd7.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include/hw/isa')
| -rw-r--r-- | include/hw/isa/i8259_internal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_internal.h index 155b098..f9dcc41 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -61,6 +61,7 @@ struct PICCommonState { uint8_t single_mode; /* true if slave pic is not initialized */ uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; + uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */ qemu_irq int_out[1]; uint32_t master; /* reflects /SP input pin */ uint32_t iobase; |