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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-20 19:49:40 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:34 +0200 |
| commit | 84c2fdc397b6609d1cef76aec2f1367139d1372e (patch) | |
| tree | 026a408aafdf5dfe159a336eb3ed22cb76d94f44 /include/hw/i2c | |
| parent | bcad139192b0101e3d7ef593144c314bed4cb8c2 (diff) | |
| download | qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.zip qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.tar.gz qemu-84c2fdc397b6609d1cef76aec2f1367139d1372e.tar.bz2 | |
target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
Diffstat (limited to 'include/hw/i2c')
0 files changed, 0 insertions, 0 deletions