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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-10-01 10:43:29 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-10-24 07:57:47 +0200 |
| commit | 404e75343c3faef7d8e042dd3ad3153a9815ade1 (patch) | |
| tree | 43e33e2107e262c32fdffb8ab4572de42d0da198 /include/hw/gpio | |
| parent | 9422dbd10b759a558de8b620ade4686d407fc63f (diff) | |
| download | qemu-404e75343c3faef7d8e042dd3ad3153a9815ade1.zip qemu-404e75343c3faef7d8e042dd3ad3153a9815ade1.tar.gz qemu-404e75343c3faef7d8e042dd3ad3153a9815ade1.tar.bz2 | |
hw/gpio/aspeed: Support different memory region ops
It set "aspeed_gpio_ops" struct which containing read and write callbacks
to be used when I/O is performed on the GPIO region.
Besides, in the previous design of ASPEED SOCs, one register is used for
setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600.
ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600.
However, the register set have a significant change in AST2700.
Each GPIO pin has their own control register. In other words, users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include/hw/gpio')
| -rw-r--r-- | include/hw/gpio/aspeed_gpio.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 8cd2ff5..e1e6c54 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -77,6 +77,7 @@ struct AspeedGPIOClass { const AspeedGPIOReg *reg_table; unsigned reg_table_count; uint64_t mem_size; + const MemoryRegionOps *reg_ops; }; struct AspeedGPIOState { |