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authorPeter Maydell <peter.maydell@linaro.org>2024-01-30 15:53:37 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-01-30 15:53:37 +0000
commit1c8e621f097362d0a28c65fa2f31054b47a5282b (patch)
treed161f9b0f9007281ebf871e6dc034fc16c462e8d /include/hw/core
parent11be70677c70fdccd452a3233653949b79e97908 (diff)
parentec1d32af123e7f13d98754a72bcaa7aa8c8e9d27 (diff)
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Merge tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu into staging
linux-user: Allow gdbstub to ignore page protection cpu-exec: simplify jump cache management include/exec: Cleanups toward building accel/tcg once # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW4LXcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+CgAf8CdqkvKsUK9/5bu99 # 9E4kRBkR8KqWYvBfRs4IFmjoEdEa4sCujWrHliOcW7Kh+XlVyAPI9rZG32QkxCEQ # hi9WXieXjfPLTTmrbeiq7cwxztSj8Z55wwvbxkrtFyGDQ0AMccp49tAvfejEb6VD # Ssx96nWQDgryLrn+My+wMQjl9aVKUWp5vB8k12aAcpRXPH2yoGE2JHAZ1C743nA6 # rShiJAT78HwERcMXDeYmmriYg0s4Z4+A6ErTiXDnFgj87YanHZc0I/55G5Sh+pW8 # REicD3jwS0GHOOHL0K781FopE1wTM442GLVxobXoxUXsHEiO+3TK5JdEIqvSstYA # fRB8Pg== # =xZOe # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jan 2024 22:57:59 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu: (31 commits) target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler accel/tcg: Inline need_replay_interrupt target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c target/loongarch: Constify loongarch_tcg_ops include/qemu: Add TCGCPUOps typedef to typedefs.h accel/tcg: Un-inline icount_exit_request() for clarity accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson accel/tcg: Move perf and debuginfo support to tcg/ accel/tcg: Remove #ifdef TARGET_I386 from perf.c tcg: Make tb_cflags() usable from target-agnostic code accel/tcg: Make use of qemu_target_page_mask() in perf.c target: Make qemu_target_page_mask() available for *-user accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD tests/tcg: Add the PROT_NONE gdbstub test tests/tcg: Factor out gdbstub test functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/core')
-rw-r--r--include/hw/core/cpu.h7
-rw-r--r--include/hw/core/tcg-cpu-ops.h19
2 files changed, 13 insertions, 13 deletions
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 238c02c..2c284d6 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -22,8 +22,8 @@
#include "hw/qdev-core.h"
#include "disas/dis-asm.h"
-#include "exec/cpu-common.h"
#include "exec/hwaddr.h"
+#include "exec/vaddr.h"
#include "exec/memattrs.h"
#include "exec/tlb-common.h"
#include "qapi/qapi-types-run-state.h"
@@ -90,9 +90,6 @@ typedef enum MMUAccessType {
typedef struct CPUWatchpoint CPUWatchpoint;
-/* see tcg-cpu-ops.h */
-struct TCGCPUOps;
-
/* see accel-cpu.h */
struct AccelCPUClass;
@@ -177,7 +174,7 @@ struct CPUClass {
const struct SysemuCPUOps *sysemu_ops;
/* when TCG is not available, this pointer is NULL */
- const struct TCGCPUOps *tcg_ops;
+ const TCGCPUOps *tcg_ops;
/*
* if not NULL, this is called in order for the CPUClass to initialize
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 479713a..bf8ff8e 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -50,7 +50,7 @@ struct TCGCPUOps {
void (*debug_excp_handler)(CPUState *cpu);
#ifdef NEED_CPU_H
-#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
+#ifdef CONFIG_USER_ONLY
/**
* @fake_user_interrupt: Callback for 'fake exception' handling.
*
@@ -58,13 +58,7 @@ struct TCGCPUOps {
* cpu execution loop (hack for x86 user mode).
*/
void (*fake_user_interrupt)(CPUState *cpu);
-#else
- /**
- * @do_interrupt: Callback for interrupt handling.
- */
- void (*do_interrupt)(CPUState *cpu);
-#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
-#ifdef CONFIG_USER_ONLY
+
/**
* record_sigsegv:
* @cpu: cpu context
@@ -114,8 +108,12 @@ struct TCGCPUOps {
void (*record_sigbus)(CPUState *cpu, vaddr addr,
MMUAccessType access_type, uintptr_t ra);
#else
+ /** @do_interrupt: Callback for interrupt handling. */
+ void (*do_interrupt)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /** @cpu_exec_halt: Callback for handling halt in cpu_exec */
+ void (*cpu_exec_halt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss
*
@@ -170,6 +168,11 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
+ /**
+ * @need_replay_interrupt: Return %true if @interrupt_request
+ * needs to be recorded for replay purposes.
+ */
+ bool (*need_replay_interrupt)(int interrupt_request);
#endif /* !CONFIG_USER_ONLY */
#endif /* NEED_CPU_H */