aboutsummaryrefslogtreecommitdiff
path: root/include/fpu
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2024-12-11 15:31:04 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-12-11 15:31:04 +0000
commit1b2de0c3c08afdb27b24d9f03aa3ba7abca432c9 (patch)
treea9c7d816276ea53be7e57d85077ed16cc5f21461 /include/fpu
parent47aa9001d8c88e75a20559d59f666878b77d1b16 (diff)
downloadqemu-1b2de0c3c08afdb27b24d9f03aa3ba7abca432c9.zip
qemu-1b2de0c3c08afdb27b24d9f03aa3ba7abca432c9.tar.gz
qemu-1b2de0c3c08afdb27b24d9f03aa3ba7abca432c9.tar.bz2
fpu: Allow runtime choice of default NaN value
Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit is different) Add a field to float_status to specify the default NaN value; fall back to the old ifdef behaviour if these are not set. The default NaN value is specified by setting a uint8_t to a pattern corresponding to the sign and upper fraction parts of the NaN; the lower bits of the fraction are set from bit 0 of the pattern. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
Diffstat (limited to 'include/fpu')
-rw-r--r--include/fpu/softfloat-helpers.h11
-rw-r--r--include/fpu/softfloat-types.h10
2 files changed, 21 insertions, 0 deletions
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
index 10a6763..dceee23 100644
--- a/include/fpu/softfloat-helpers.h
+++ b/include/fpu/softfloat-helpers.h
@@ -93,6 +93,12 @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
status->float_infzeronan_rule = rule;
}
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
+ float_status *status)
+{
+ status->default_nan_pattern = dnan_pattern;
+}
+
static inline void set_flush_to_zero(bool val, float_status *status)
{
status->flush_to_zero = val;
@@ -154,6 +160,11 @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
return status->float_infzeronan_rule;
}
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
+{
+ return status->default_nan_pattern;
+}
+
static inline bool get_flush_to_zero(float_status *status)
{
return status->flush_to_zero;
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 84ba4ed..79ca44d 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -304,6 +304,16 @@ typedef struct float_status {
bool flush_inputs_to_zero;
bool default_nan_mode;
/*
+ * The pattern to use for the default NaN. Here the high bit specifies
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
+ * fractional part. The low bits of the fractional part are copies of bit 0.
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
+ * Note that a value of 0 here is not a valid NaN. The target must set
+ * this to the correct non-zero value, or we will assert when trying to
+ * create a default NaN.
+ */
+ uint8_t default_nan_pattern;
+ /*
* The flags below are not used on all specializations and may
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
* softfloat-specialize.inc.c)