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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-07-02 17:57:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-02 17:57:46 +0100 |
| commit | ab08440a4ee09032d1a9cb22fdcab23bc7e1c656 (patch) | |
| tree | 1ecb443a3b08cbe09a0f1864cd7feb9f42f23da8 /include/exec/cpu-all.h | |
| parent | e14dcc9cda9858e169b8387ec0a93077d75d4faa (diff) | |
| parent | 9c8c334b0637bf3c592d432b0c11f3b62dd5dba3 (diff) | |
| download | qemu-ab08440a4ee09032d1a9cb22fdcab23bc7e1c656.zip qemu-ab08440a4ee09032d1a9cb22fdcab23bc7e1c656.tar.gz qemu-ab08440a4ee09032d1a9cb22fdcab23bc7e1c656.tar.bz2 | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180702' into staging
Assorted tlb and tb caching fixes
# gpg: Signature made Mon 02 Jul 2018 17:03:07 BST
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20180702:
cpu: Assert asidx_from_attrs return value in range
accel/tcg: Avoid caching overwritten tlb entries
accel/tcg: Don't treat invalid TLB entries as needing recheck
accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()
tcg: Define and use new tlb_hit() and tlb_hit_page() functions
translate-all: fix locking of TBs whose two pages share the same physical page
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec/cpu-all.h')
| -rw-r--r-- | include/exec/cpu-all.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 7338f57..117d2fb 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -339,6 +339,29 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ | TLB_RECHECK) +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) +{ + return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); #endif /* !CONFIG_USER_ONLY */ |