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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-05-24 13:32:55 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-30 13:21:06 +0100 |
| commit | f5e328fef057a79ee40a93cdb27bf0de7991973e (patch) | |
| tree | e41221fbab01eadd895f1f25d2c2c74eef3d246d /hw | |
| parent | 3b2fe44bb7f605f179e5e7feb2c13c2eb3abbb80 (diff) | |
| download | qemu-f5e328fef057a79ee40a93cdb27bf0de7991973e.zip qemu-f5e328fef057a79ee40a93cdb27bf0de7991973e.tar.gz qemu-f5e328fef057a79ee40a93cdb27bf0de7991973e.tar.bz2 | |
hw/intc/arm_gic: Fix set pending of PPIs
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524113256.8102-2-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/arm_gic.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index e4b8437..04e5a11 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1308,12 +1308,15 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, for (i = 0; i < 8; i++) { if (value & (1 << i)) { + int mask = (irq < GIC_INTERNAL) ? (1 << cpu) + : GIC_DIST_TARGET(irq + i); + if (s->security_extn && !attrs.secure && !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { continue; /* Ignore Non-secure access of Group0 IRQ */ } - GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); + GIC_DIST_SET_PENDING(irq + i, mask); } } } else if (offset < 0x300) { |