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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-10-01 10:43:32 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-10-24 07:57:47 +0200 |
| commit | f34030ec7e2672d811bf60e2922f8487d74e3980 (patch) | |
| tree | ea6186153d604adfccea8de902bad743d0e5bf21 /hw | |
| parent | bac698832de3160e3327a007a86958be08ecbd35 (diff) | |
| download | qemu-f34030ec7e2672d811bf60e2922f8487d74e3980.zip qemu-f34030ec7e2672d811bf60e2922f8487d74e3980.tar.gz qemu-f34030ec7e2672d811bf60e2922f8487d74e3980.tar.bz2 | |
aspeed/soc: Correct GPIO irq 130 for AST2700
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO 1.8v, removes
ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO
device in AST2700.
The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/aspeed_ast27x0.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 761ee11..99135ed 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -87,8 +87,7 @@ static const int aspeed_soc_ast2700_irqmap[] = { [ASPEED_DEV_ADC] = 130, [ASPEED_DEV_XDMA] = 5, [ASPEED_DEV_EMMC] = 15, - [ASPEED_DEV_GPIO] = 11, - [ASPEED_DEV_GPIO_1_8V] = 130, + [ASPEED_DEV_GPIO] = 130, [ASPEED_DEV_RTC] = 13, [ASPEED_DEV_TIMER1] = 16, [ASPEED_DEV_TIMER2] = 17, @@ -124,7 +123,7 @@ static const int aspeed_soc_ast2700_gic128_intcmap[] = { static const int aspeed_soc_ast2700_gic130_intcmap[] = { [ASPEED_DEV_I2C] = 0, [ASPEED_DEV_ADC] = 16, - [ASPEED_DEV_GPIO_1_8V] = 18, + [ASPEED_DEV_GPIO] = 18, }; /* GICINT 131 */ |