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authorDavid Gibson <david@gibson.dropbear.id.au>2018-05-01 16:08:50 +1000
committerDavid Gibson <david@gibson.dropbear.id.au>2018-05-04 15:00:37 +1000
commitf00bed9521cee4d67c4937b51de692e0bcf9efef (patch)
treedb38b9c0f3d4a84144f655695fc3a1097d995e35 /hw
parent295b6c26aca97c5f6f6609f62d958af6af848454 (diff)
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target/ppc: Delay initialization of LPCR_UPRT for secondary cpus
In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are initialized based on on ppc64_radix_guest(). Which seems reasonable, except that ppc64_radix_guest() is based on spapr->patb_entry which is only set up in spapr_machine_reset, called _after_ cpu_ppc_set_papr() for boot cpus. Well, and the fact that modifying the SPR default value for an instance rather than a class is kind of yucky. The initialization here is really only necessary or valid for hotplugged cpus; the base cpu initialization already sets a value that's good enough for the boot cpus until the guest uses an hcall to configure it's preferred MMU mode. So, move this initialization to the rtas_start_cpu() path, at which point ppc64_radix_guest() will have a sensible value, to make sure secondary cpus come up in an MMU mode matching the existing cpus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/ppc/spapr_rtas.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 840d198..652233b 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -47,6 +47,7 @@
#include "trace.h"
#include "hw/ppc/fdt.h"
#include "target/ppc/mmu-hash64.h"
+#include "target/ppc/mmu-book3s-v3.h"
static void rtas_display_character(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -165,6 +166,17 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMachineState *spapr,
if (!pcc->interrupts_big_endian(callcpu)) {
lpcr |= LPCR_ILE;
}
+ if (env->mmu_model == POWERPC_MMU_3_00) {
+ /*
+ * New cpus are expected to start in the same radix/hash mode
+ * as the existing CPUs
+ */
+ if (ppc64_radix_guest(callcpu)) {
+ lpcr |= LPCR_UPRT | LPCR_GTSE;
+ } else {
+ lpcr &= ~(LPCR_UPRT | LPCR_GTSE);
+ }
+ }
ppc_store_lpcr(newcpu, lpcr);
/*