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author | Blue Swirl <blauwirbel@gmail.com> | 2012-11-03 12:55:05 +0000 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-11-03 12:55:05 +0000 |
commit | ef84755ebb38b4f5629b24440bb00f1ef5287707 (patch) | |
tree | c2d74584b5f8c85c4c61ae650e628e08403b69ec /hw | |
parent | b76f0d8c2e3eac94bc7fd90a510cb7426b2a2699 (diff) | |
parent | 0d3cf3b6ff469bba95ae235021a3be232af4068d (diff) | |
download | qemu-ef84755ebb38b4f5629b24440bb00f1ef5287707.zip qemu-ef84755ebb38b4f5629b24440bb00f1ef5287707.tar.gz qemu-ef84755ebb38b4f5629b24440bb00f1ef5287707.tar.bz2 |
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
* 'trivial-patches' of git://github.com/stefanha/qemu:
pc: Drop redundant test for ROM memory region
exec: make some functions static
target-ppc: make some functions static
ppc: add missing static
vnc: add missing static
vl.c: add missing static
target-sparc: make do_unaligned_access static
m68k: Return semihosting errno values correctly
cadence_uart: More debug information
Conflicts:
target-m68k/m68k-semi.c
Diffstat (limited to 'hw')
-rw-r--r-- | hw/adb.c | 8 | ||||
-rw-r--r-- | hw/adb.h | 4 | ||||
-rw-r--r-- | hw/cadence_uart.c | 11 | ||||
-rw-r--r-- | hw/nvram.h | 10 | ||||
-rw-r--r-- | hw/pc_piix.c | 2 | ||||
-rw-r--r-- | hw/ppc.c | 16 |
6 files changed, 21 insertions, 30 deletions
@@ -108,10 +108,10 @@ int adb_poll(ADBBusState *s, uint8_t *obuf) return olen; } -ADBDevice *adb_register_device(ADBBusState *s, int devaddr, - ADBDeviceRequest *devreq, - ADBDeviceReset *devreset, - void *opaque) +static ADBDevice *adb_register_device(ADBBusState *s, int devaddr, + ADBDeviceRequest *devreq, + ADBDeviceReset *devreset, + void *opaque) { ADBDevice *d; if (s->nb_devices >= MAX_ADB_DEVICES) @@ -56,10 +56,6 @@ int adb_request(ADBBusState *s, uint8_t *buf_out, const uint8_t *buf, int len); int adb_poll(ADBBusState *s, uint8_t *buf_out); -ADBDevice *adb_register_device(ADBBusState *s, int devaddr, - ADBDeviceRequest *devreq, - ADBDeviceReset *devreset, - void *opaque); void adb_kbd_init(ADBBusState *bus); void adb_mouse_init(ADBBusState *bus); diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c index a7d0504..686e617 100644 --- a/hw/cadence_uart.c +++ b/hw/cadence_uart.c @@ -359,7 +359,7 @@ static void uart_write(void *opaque, hwaddr offset, { UartState *s = (UartState *)opaque; - DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value); + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; switch (offset) { case R_IER: /* ier (wts imr) */ @@ -405,12 +405,15 @@ static uint64_t uart_read(void *opaque, hwaddr offset, offset >>= 2; if (offset >= R_MAX) { - return 0; + c = 0; } else if (offset == R_TX_RX) { uart_read_rx_fifo(s, &c); - return c; + } else { + c = s->r[offset]; } - return s->r[offset]; + + DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); + return c; } static const MemoryRegionOps uart_ops = { @@ -10,17 +10,9 @@ typedef struct nvram_t { nvram_write_t write_fn; } nvram_t; -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value); -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr); -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value); -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr); -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value); uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr); -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, - const char *str, uint32_t max); int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max); -void NVRAM_set_crc (nvram_t *nvram, uint32_t addr, - uint32_t start, uint32_t count); + int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, const char *arch, uint32_t RAM_size, int boot_device, diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 85529b2..cfa839c 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -178,7 +178,7 @@ static void pc_init1(MemoryRegion *system_memory, fw_cfg = pc_memory_init(system_memory, kernel_filename, kernel_cmdline, initrd_filename, below_4g_mem_size, above_4g_mem_size, - pci_enabled ? rom_memory : system_memory, &ram_memory); + rom_memory, &ram_memory); } gsi_state = g_malloc0(sizeof(*gsi_state)); @@ -736,7 +736,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value) +static void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) { ppc_tb_t *tb_env = env->tb_env; @@ -1167,23 +1167,23 @@ static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) (*nvram->write_fn)(nvram->opaque, addr, val); } -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) +static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value) { nvram_write(nvram, addr, value); } -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) +static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr) { return nvram_read(nvram, addr); } -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) +static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value) { nvram_write(nvram, addr, value >> 8); nvram_write(nvram, addr + 1, value & 0xFF); } -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) +static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr) { uint16_t tmp; @@ -1193,7 +1193,7 @@ uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) +static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value) { nvram_write(nvram, addr, value >> 24); nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); @@ -1213,8 +1213,8 @@ uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, - const char *str, uint32_t max) +static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str, + uint32_t max) { int i; |