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authorPeter Maydell <peter.maydell@linaro.org>2017-02-13 09:30:15 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-13 09:30:15 +0000
commited3d90df7c75203d9d4bae135f0a3c75be209f78 (patch)
treef339a333fa1d8906b90f1d5d4554d01f01ca4f09 /hw
parent6311b19b5c650388745aafe1269489bd5afe4f2d (diff)
parente197de50c6cfad69d2c26c22693b57678ae99d14 (diff)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20170210.0' into staging
VFIO updates 2017-02-10 - Fix GTT wrap-around for Skylake IGD assignment (Alex Williamson) - Tag vfio-pci-igd-lpc-bridge as bridge device category (Thomas Huth) - Don't build calxeda-xgmac or amd-xgbe except on ARM (Thomas Huth) # gpg: Signature made Fri 10 Feb 2017 21:34:33 GMT # gpg: using RSA key 0x239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-updates-20170210.0: hw/vfio: Add CONFIG switches for calxeda-xgmac and amd-xgbe hw/vfio/pci-quirks: Set category of the "vfio-pci-igd-lpc-bridge" device vfio-pci: Fix GTT wrap-around for Skylake+ IGD Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/vfio/Makefile.objs4
-rw-r--r--hw/vfio/pci-quirks.c6
2 files changed, 7 insertions, 3 deletions
diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs
index c25e32b..05e7fbb 100644
--- a/hw/vfio/Makefile.objs
+++ b/hw/vfio/Makefile.objs
@@ -2,7 +2,7 @@ ifeq ($(CONFIG_LINUX), y)
obj-$(CONFIG_SOFTMMU) += common.o
obj-$(CONFIG_PCI) += pci.o pci-quirks.o
obj-$(CONFIG_SOFTMMU) += platform.o
-obj-$(CONFIG_SOFTMMU) += calxeda-xgmac.o
-obj-$(CONFIG_SOFTMMU) += amd-xgbe.o
+obj-$(CONFIG_VFIO_XGMAC) += calxeda-xgmac.o
+obj-$(CONFIG_VFIO_AMD_XGBE) += amd-xgbe.o
obj-$(CONFIG_SOFTMMU) += spapr.o
endif
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index 6c771f7..e9b493b 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1041,6 +1041,7 @@ static int igd_gen(VFIOPCIDevice *vdev)
typedef struct VFIOIGDQuirk {
struct VFIOPCIDevice *vdev;
uint32_t index;
+ uint32_t bdsm;
} VFIOIGDQuirk;
#define IGD_GMCH 0x50 /* Graphics Control Register */
@@ -1185,6 +1186,7 @@ static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment";
dc->hotpluggable = false;
k->realize = vfio_pci_igd_lpc_bridge_realize;
@@ -1304,7 +1306,7 @@ static void vfio_igd_quirk_data_write(void *opaque, hwaddr addr,
"BIOS reserved stolen memory. Unsupported BIOS?");
}
- val = base | (data & ((1 << 20) - 1));
+ val = data - igd->bdsm + base;
} else {
val = 0; /* upper 32bits of pte, we only enable below 4G PTEs */
}
@@ -1503,6 +1505,8 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
igd = quirk->data = g_malloc0(sizeof(*igd));
igd->vdev = vdev;
igd->index = ~0;
+ igd->bdsm = vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4);
+ igd->bdsm &= ~((1 << 20) - 1); /* 1MB aligned */
memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk,
igd, "vfio-igd-index-quirk", 4);