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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-11-01 16:33:24 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-05 23:32:25 +0000 |
| commit | e823ebe77d8f38b181a3c277d5dd9399748bf566 (patch) | |
| tree | 8e6942357c6c37da32aa28b182600779dd81f5d0 /hw | |
| parent | 34230ce5a97b898a53032b958841e74fde0bdac1 (diff) | |
| download | qemu-e823ebe77d8f38b181a3c277d5dd9399748bf566.zip qemu-e823ebe77d8f38b181a3c277d5dd9399748bf566.tar.gz qemu-e823ebe77d8f38b181a3c277d5dd9399748bf566.tar.bz2 | |
hw/core: Make CPU topology enumeration arch-agnostic
Cache topology needs to be defined based on CPU topology levels. Thus,
define CPU topology enumeration in qapi/machine.json to make it generic
for all architectures.
To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
socket.
Also, enumerate additional topology levels for non-i386 arches, and add
a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
with compatibility requirement of arch-specific cache topology models.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241101083331.340178-3-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i386/x86-common.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index b86c382..bc360a9 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, if (ms->smp.modules > 1) { env->nr_modules = ms->smp.modules; - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); } if (ms->smp.dies > 1) { env->nr_dies = ms->smp.dies; - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo); } /* |