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author | Thomas Huth <thuth@redhat.com> | 2023-09-07 13:35:00 +0200 |
---|---|---|
committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-08 13:08:52 +0300 |
commit | ded625e7aa6a7f3173a22657f7dc0e9ab3d8fa3b (patch) | |
tree | 21c63bb1e087b0a4aa1cc1e6c4e6f25ef84c68e4 /hw | |
parent | d417e2214d3adfd862bdf7afb3392e7f9de7fc05 (diff) | |
download | qemu-ded625e7aa6a7f3173a22657f7dc0e9ab3d8fa3b.zip qemu-ded625e7aa6a7f3173a22657f7dc0e9ab3d8fa3b.tar.gz qemu-ded625e7aa6a7f3173a22657f7dc0e9ab3d8fa3b.tar.bz2 |
trivial: Simplify the spots that use TARGET_BIG_ENDIAN as a numeric value
TARGET_BIG_ENDIAN is *always* defined, either as 0 for little endian
targets or as 1 for big endian targets. So we can use this as a value
directly in places that need such a 0 or 1 for some reason, instead
of taking a detour through an additional local variable or something
similar.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/microblaze/boot.c | 9 | ||||
-rw-r--r-- | hw/mips/jazz.c | 10 | ||||
-rw-r--r-- | hw/mips/malta.c | 21 | ||||
-rw-r--r-- | hw/mips/mipssim.c | 9 | ||||
-rw-r--r-- | hw/nios2/boot.c | 9 | ||||
-rw-r--r-- | hw/xtensa/sim.c | 7 | ||||
-rw-r--r-- | hw/xtensa/xtfpga.c | 10 |
7 files changed, 15 insertions, 60 deletions
diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index 25ad547..ed61e48 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -140,22 +140,17 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, int kernel_size; uint64_t entry, high; uint32_t base32; - int big_endian = 0; - -#if TARGET_BIG_ENDIAN - big_endian = 1; -#endif /* Boots a kernel elf binary. */ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &entry, NULL, &high, NULL, - big_endian, EM_MICROBLAZE, 0, 0); + TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); base32 = entry; if (base32 == 0xc0000000) { kernel_size = load_elf(kernel_filename, NULL, translate_kernel_address, NULL, &entry, NULL, NULL, NULL, - big_endian, EM_MICROBLAZE, 0, 0); + TARGET_BIG_ENDIAN, EM_MICROBLAZE, 0, 0); } /* Always boot into physical ram. */ boot_info.bootstrap_pc = (uint32_t)entry; diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index ca4426a..0081dcf 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -125,7 +125,7 @@ static void mips_jazz_init(MachineState *machine, { MemoryRegion *address_space = get_system_memory(); char *filename; - int bios_size, n, big_endian; + int bios_size, n; Clock *cpuclk; MIPSCPU *cpu; MIPSCPUClass *mcc; @@ -157,12 +157,6 @@ static void mips_jazz_init(MachineState *machine, [JAZZ_PICA61] = {33333333, 4}, }; -#if TARGET_BIG_ENDIAN - big_endian = 1; -#else - big_endian = 0; -#endif - if (machine->ram_size > 256 * MiB) { error_report("RAM size more than 256Mb is not supported"); exit(EXIT_FAILURE); @@ -301,7 +295,7 @@ static void mips_jazz_init(MachineState *machine, dev = qdev_new("dp8393x"); qdev_set_nic_properties(dev, nd); qdev_prop_set_uint8(dev, "it_shift", 2); - qdev_prop_set_bit(dev, "big_endian", big_endian > 0); + qdev_prop_set_bit(dev, "big_endian", TARGET_BIG_ENDIAN); object_property_set_link(OBJECT(dev), "dma_mr", OBJECT(rc4030_dma_mr), &error_abort); sysbus = SYS_BUS_DEVICE(dev); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 16e9c47..dac27fa 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -870,7 +870,6 @@ static uint64_t load_kernel(void) uint64_t kernel_entry, kernel_high, initrd_size; long kernel_size; ram_addr_t initrd_offset; - int big_endian; uint32_t *prom_buf; long prom_size; int prom_index = 0; @@ -878,16 +877,10 @@ static uint64_t load_kernel(void) char rng_seed_hex[sizeof(rng_seed) * 2 + 1]; size_t rng_seed_prom_offset; -#if TARGET_BIG_ENDIAN - big_endian = 1; -#else - big_endian = 0; -#endif - kernel_size = load_elf(loaderparams.kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, &kernel_entry, NULL, - &kernel_high, NULL, big_endian, EM_MIPS, + &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS, 1, 0); if (kernel_size < 0) { error_report("could not load kernel '%s': %s", @@ -1107,7 +1100,6 @@ void mips_malta_init(MachineState *machine) I2CBus *smbus; DriveInfo *dinfo; int fl_idx = 0; - int be; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1144,12 +1136,6 @@ void mips_malta_init(MachineState *machine) ram_low_postio); } -#if TARGET_BIG_ENDIAN - be = 1; -#else - be = 0; -#endif - /* FPGA */ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ @@ -1161,7 +1147,8 @@ void mips_malta_init(MachineState *machine) FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 65536, - 4, 0x0000, 0x0000, 0x0000, 0x0000, be); + 4, 0x0000, 0x0000, 0x0000, 0x0000, + TARGET_BIG_ENDIAN); bios = pflash_cfi01_get_memory(fl); fl_idx++; if (kernel_filename) { @@ -1245,7 +1232,7 @@ void mips_malta_init(MachineState *machine) /* Northbridge */ dev = qdev_new("gt64120"); - qdev_prop_set_bit(dev, "cpu-little-endian", !be); + qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 39f6444..2f951f7 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -62,18 +62,11 @@ static uint64_t load_kernel(void) uint64_t entry, kernel_high, initrd_size; long kernel_size; ram_addr_t initrd_offset; - int big_endian; - -#if TARGET_BIG_ENDIAN - big_endian = 1; -#else - big_endian = 0; -#endif kernel_size = load_elf(loaderparams.kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, &entry, NULL, - &kernel_high, NULL, big_endian, + &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS, 1, 0); if (kernel_size < 0) { error_report("could not load kernel '%s': %s", diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index b30a7b1..cd75803 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -148,16 +148,11 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, if (kernel_filename) { int kernel_size, fdt_size; uint64_t entry, high; - int big_endian = 0; - -#if TARGET_BIG_ENDIAN - big_endian = 1; -#endif /* Boots a kernel elf binary. */ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &entry, NULL, &high, NULL, - big_endian, EM_ALTERA_NIOS2, 0, 0); + TARGET_BIG_ENDIAN, EM_ALTERA_NIOS2, 0, 0); if ((uint32_t)entry == 0xc0000000) { /* * The Nios II processor reference guide documents that the @@ -168,7 +163,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, kernel_size = load_elf(kernel_filename, NULL, translate_kernel_address, NULL, &entry, NULL, NULL, NULL, - big_endian, EM_ALTERA_NIOS2, 0, 0); + TARGET_BIG_ENDIAN, EM_ALTERA_NIOS2, 0, 0); boot_info.bootstrap_pc = ddr_base + 0xc0000000 + (entry & 0x07ffffff); } else { diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 946c71c..2160e61 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -96,16 +96,11 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine) void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine) { const char *kernel_filename = machine->kernel_filename; -#if TARGET_BIG_ENDIAN - int big_endian = true; -#else - int big_endian = false; -#endif if (kernel_filename) { uint64_t elf_entry; int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, - &elf_entry, NULL, NULL, NULL, big_endian, + &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN, EM_XTENSA, 0, 0); if (success > 0) { diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 2a5556a..fbad1c8 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -219,11 +219,6 @@ static const MemoryRegionOps xtfpga_io_ops = { static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) { -#if TARGET_BIG_ENDIAN - int be = 1; -#else - int be = 0; -#endif MemoryRegion *system_memory = get_system_memory(); XtensaCPU *cpu = NULL; CPUXtensaState *env = NULL; @@ -316,7 +311,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { - flash = xtfpga_flash_init(system_io, board, dinfo, be); + flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); } /* Use presence of kernel file name as 'boot from SRAM' switch. */ @@ -412,7 +407,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) uint64_t elf_entry; int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, - &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); + &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN, + EM_XTENSA, 0, 0); if (success > 0) { entry_point = elf_entry; } else { |