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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-04-09 16:05:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-12 15:57:18 +0100 |
| commit | db2fc83aa45a391fa0eb9caa2728f5aa9225d4cc (patch) | |
| tree | e21c309ee1d738ee9c646c844cd3fa5d101ce5d2 /hw | |
| parent | c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620 (diff) | |
| download | qemu-db2fc83aa45a391fa0eb9caa2728f5aa9225d4cc.zip qemu-db2fc83aa45a391fa0eb9caa2728f5aa9225d4cc.tar.gz qemu-db2fc83aa45a391fa0eb9caa2728f5aa9225d4cc.tar.bz2 | |
hw/arm/mps2-tz: Fix MPC setting for AN524 SRAM block
The AN524 has three MPCs: one for the BRAM, one for the QSPI flash,
and one for the DDR. We incorrectly set the .mpc field in the
RAMInfo struct for the SRAM block to 1, giving it the same MPC we are
using for the QSPI. The effect of this was that the QSPI didn't get
mapped into the system address space at all, via an MPC or otherwise,
and guest programs which tried to read from the QSPI would get a bus
error. Correct the SRAM RAMInfo to indicate that it does not have an
associated MPC.
Fixes: 25ff112a8cc ("hw/arm/mps2-tz: Add new mps3-an524 board")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210409150527.15053-2-peter.maydell@linaro.org
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/mps2-tz.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3fbe3d2..5ebd671 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -238,7 +238,7 @@ static const RAMInfo an524_raminfo[] = { { .name = "sram", .base = 0x20000000, .size = 32 * 4 * KiB, - .mpc = 1, + .mpc = -1, .mrindex = 1, }, { /* We don't model QSPI flash yet; for now expose it as simple ROM */ |