diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2021-10-14 21:50:19 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-10-21 11:42:47 +1100 |
| commit | d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d (patch) | |
| tree | 2fec16ecc1feb05139d9b432330f3cb9b4d8585b /hw | |
| parent | bd20cde50bb1a3b47fcba02432edc6141d9fb1d0 (diff) | |
| download | qemu-d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d.zip qemu-d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d.tar.gz qemu-d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d.tar.bz2 | |
ppc/pegasos2: Add constants for PCI config addresses
Define a constant for PCI config addresses to make it clearer what
these numbers are.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ppc/pegasos2.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index a861bf1..39e96d3 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -54,11 +54,13 @@ #define BUS_FREQ_HZ 133333333 +#define PCI0_CFG_ADDR 0xcf8 #define PCI0_MEM_BASE 0xc0000000 #define PCI0_MEM_SIZE 0x20000000 #define PCI0_IO_BASE 0xf8000000 #define PCI0_IO_SIZE 0x10000 +#define PCI1_CFG_ADDR 0xc78 #define PCI1_MEM_BASE 0x80000000 #define PCI1_MEM_SIZE 0x40000000 #define PCI1_IO_BASE 0xfe000000 @@ -226,7 +228,7 @@ static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, uint32_t addr, uint32_t len) { - hwaddr pcicfg = bus ? 0xc78 : 0xcf8; + hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; uint64_t val = 0xffffffffULL; if (len <= 4) { @@ -239,7 +241,7 @@ static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, uint32_t addr, uint32_t len, uint32_t val) { - hwaddr pcicfg = bus ? 0xc78 : 0xcf8; + hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); |