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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2022-10-12 15:59:10 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2022-10-12 15:59:10 -0400 |
| commit | cdda364e1da45edcb70fad7fa77bd2bb5e6c023f (patch) | |
| tree | 34ac767f482da3f14a5a8ab2b3d0ab962a72a3dc /hw | |
| parent | 7fa24b8d61be040ba58bed6fc1c16fd5fb7b6af0 (diff) | |
| parent | 915f62844cf62e428c7c178149b5ff1cbe129b07 (diff) | |
| download | qemu-cdda364e1da45edcb70fad7fa77bd2bb5e6c023f.zip qemu-cdda364e1da45edcb70fad7fa77bd2bb5e6c023f.tar.gz qemu-cdda364e1da45edcb70fad7fa77bd2bb5e6c023f.tar.bz2 | |
Merge tag 'pull-target-arm-20221010' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Retry KVM_CREATE_VM call if it fails EINTR
* allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
* docs/nuvoton: Update URL for images
* refactoring of page table walk code
* hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
* Don't allow guest to use unimplemented granule sizes
* Report FEAT_GTG support
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# gpg: Signature made Mon 10 Oct 2022 10:26:38 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221010' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
docs/system/arm/emulation.rst: Report FEAT_GTG support
target/arm: Use ARMGranuleSize in ARMVAParameters
target/arm: Don't allow guest to use unimplemented granule sizes
hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
target/arm: Use tlb_set_page_full
target/arm: Fix cacheattr in get_phys_addr_disabled
target/arm: Split out get_phys_addr_disabled
target/arm: Fix ATS12NSO* from S PL1
target/arm: Pass HCR to attribute subroutines.
target/arm: Remove env argument from combined_attrs_fwb
target/arm: Hoist read of *is_secure in S1_ptw_translate
target/arm: Introduce arm_hcr_el2_eff_secstate
target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
target/arm: Reorg regime_translation_disabled
target/arm: Fold secure and non-secure a-profile mmu indexes
target/arm: Add is_secure parameter to do_ats_write
target/arm: Merge regime_is_secure into get_phys_addr
target/arm: Add TBFLAG_M32.SECURE
target/arm: Add is_secure parameter to v7m_read_half_insn
target/arm: Split out get_phys_addr_with_secure
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/boot.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ada2717..ee3858b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; } + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; + env->cp15.scr_el3 |= SCR_ENTP2; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: |