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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2016-03-15 09:59:27 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-03-30 09:13:59 +0100 |
| commit | c870e3f52cac0c8a4a1377398327c4ff20d49d41 (patch) | |
| tree | 2756e94fce28c6ca90448734ea62d66e20b9b80f /hw | |
| parent | 8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3 (diff) | |
| download | qemu-c870e3f52cac0c8a4a1377398327c4ff20d49d41.zip qemu-c870e3f52cac0c8a4a1377398327c4ff20d49d41.tar.gz qemu-c870e3f52cac0c8a4a1377398327c4ff20d49d41.tar.bz2 | |
target-mips: add CMGCRBase register
Physical base address for the memory-mapped Coherency Manager Global
Configuration Register space.
The MIPS default location for the GCR_BASE address is 0x1FBF_8.
This register only exists if Config3 CMGCR is set to one.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: move CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions