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| author | Tobias Röhmel <tobias.roehmel@rwth-aachen.de> | 2022-12-06 11:24:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-05 11:51:09 +0000 |
| commit | c7f786abe2eb2f57d363e76ff992de863e998e1e (patch) | |
| tree | dbe945bd20fa82ca133944166fc981cc2b728712 /hw | |
| parent | 9e65f4e6da56e1c21af9f877e29d9db3a243b7f9 (diff) | |
| download | qemu-c7f786abe2eb2f57d363e76ff992de863e998e1e.zip qemu-c7f786abe2eb2f57d363e76ff992de863e998e1e.tar.gz qemu-c7f786abe2eb2f57d363e76ff992de863e998e1e.tar.bz2 | |
target/arm: Don't add all MIDR aliases for cores that implement PMSA
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions