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author | Richard Henderson <richard.henderson@linaro.org> | 2021-10-16 11:16:28 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-10-16 11:16:28 -0700 |
commit | c148a0572130ff485cd2249fbdd1a3260d5e10a4 (patch) | |
tree | 576984e72885c3c45e0ba8f82716f6c3f4fa4fb4 /hw | |
parent | 6587b0c1331d427b0939c37e763842550ed581db (diff) | |
parent | 995b87dedc78b0467f5f18bbc3546072ba97516a (diff) | |
download | qemu-c148a0572130ff485cd2249fbdd1a3260d5e10a4.zip qemu-c148a0572130ff485cd2249fbdd1a3260d5e10a4.tar.gz qemu-c148a0572130ff485cd2249fbdd1a3260d5e10a4.tar.bz2 |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into staging
Move gdb singlestep to generic code
Fix cpu_common_props
# gpg: Signature made Sat 16 Oct 2021 11:13:54 AM PDT
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* remotes/rth/tags/pull-tcg-20211016: (24 commits)
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
target/xtensa: Drop check for singlestep_enabled
target/tricore: Drop check for singlestep_enabled
target/sh4: Drop check for singlestep_enabled
target/s390x: Drop check for singlestep_enabled
target/rx: Drop checks for singlestep_enabled
target/riscv: Remove exit_tb and lookup_and_goto_ptr
target/riscv: Remove dead code after exception
target/ppc: Drop exit checks for singlestep_enabled
target/openrisc: Drop checks for singlestep_enabled
target/mips: Drop exit checks for singlestep_enabled
target/mips: Fix single stepping
target/microblaze: Drop checks for singlestep_enabled
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
target/m68k: Drop checks for singlestep_enabled
target/i386: Drop check for singlestep_enabled
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
target/hppa: Drop checks for singlestep_enabled
target/arm: Drop checks for singlestep_enabled
target/hexagon: Drop checks for singlestep_enabled
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/core/cpu-common.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64..9e3241b 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -257,21 +257,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } -static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY - /* Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), - DEFINE_PROP_END_OF_LIST(), -}; - static void cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -286,7 +271,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; dc->reset = cpu_common_reset; - device_class_set_props(dc, cpu_common_props); + cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up * IRQs, adding reset handlers, halting non-first CPUs, ... |