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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2023-11-01 21:45:38 +0100 |
|---|---|---|
| committer | Marc-André Lureau <marcandre.lureau@redhat.com> | 2023-11-06 15:58:43 +0400 |
| commit | bf9ac62a92ac087e44958ec18f795edfd2bf020a (patch) | |
| tree | 9429efdff1ff60ad0ff6ceb8c46d11081a7eae70 /hw | |
| parent | e876b3400a01c5f3947de34d6c10388f43192dc9 (diff) | |
| download | qemu-bf9ac62a92ac087e44958ec18f795edfd2bf020a.zip qemu-bf9ac62a92ac087e44958ec18f795edfd2bf020a.tar.gz qemu-bf9ac62a92ac087e44958ec18f795edfd2bf020a.tar.bz2 | |
ati-vga: Add 30 bit palette access register
Radeon cards have a 30 bit DAC and corresponding palette register to
access it. We only use 8 bits but let the guests use 10 bit color
values for those that access it through this register.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <9fa19eec95d1563cc65853cf26912f230c702b32.1698871239.git.balaton@eik.bme.hu>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/display/ati.c | 9 | ||||
| -rw-r--r-- | hw/display/ati_dbg.c | 1 | ||||
| -rw-r--r-- | hw/display/ati_int.h | 1 | ||||
| -rw-r--r-- | hw/display/ati_regs.h | 1 |
4 files changed, 12 insertions, 0 deletions
diff --git a/hw/display/ati.c b/hw/display/ati.c index 538651c..4868f95 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -339,6 +339,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) case PALETTE_DATA: val = vga_ioport_read(&s->vga, VGA_PEL_D); break; + case PALETTE_30_DATA: + val = s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IR)]; + break; case CNFG_CNTL: val = s->regs.config_cntl; break; @@ -673,6 +676,12 @@ static void ati_mm_write(void *opaque, hwaddr addr, data >>= 8; vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); break; + case PALETTE_30_DATA: + s->regs.palette[vga_ioport_read(&s->vga, VGA_PEL_IW)] = data; + vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 22) & 0xff); + vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 12) & 0xff); + vga_ioport_write(&s->vga, VGA_PEL_D, (data >> 2) & 0xff); + break; case CNFG_CNTL: s->regs.config_cntl = data; break; diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index 4aec1c3..3ffa7f3 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -30,6 +30,7 @@ static struct ati_regdesc ati_reg_names[] = { {"AMCGPIO_EN_MIR", 0x00a8}, {"PALETTE_INDEX", 0x00b0}, {"PALETTE_DATA", 0x00b4}, + {"PALETTE_30_DATA", 0x00b8}, {"CNFG_CNTL", 0x00e0}, {"GEN_RESET_CNTL", 0x00f0}, {"CNFG_MEMSIZE", 0x00f8}, diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index e8d3c7a..8abb873 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -44,6 +44,7 @@ typedef struct ATIVGARegs { uint32_t gpio_dvi_ddc; uint32_t gpio_monid; uint32_t config_cntl; + uint32_t palette[256]; uint32_t crtc_h_total_disp; uint32_t crtc_h_sync_strt_wid; uint32_t crtc_v_total_disp; diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index c697b32..d712774 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -48,6 +48,7 @@ #define AMCGPIO_EN_MIR 0x00a8 #define PALETTE_INDEX 0x00b0 #define PALETTE_DATA 0x00b4 +#define PALETTE_30_DATA 0x00b8 #define CNFG_CNTL 0x00e0 #define GEN_RESET_CNTL 0x00f0 #define CNFG_MEMSIZE 0x00f8 |