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authorTao Xu <tao3.xu@intel.com>2018-12-27 10:43:03 +0800
committerEduardo Habkost <ehabkost@redhat.com>2019-01-28 15:51:54 -0200
commitb0a1980384fc265d91de7e09aa5fe531a69e6288 (patch)
tree21dd6e076bc8ed884cac674b3adba40ca1bac7de /hw
parent5f39a91dbd9a186edb999afd4d17524f4b1da14f (diff)
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i386: Update stepping of Cascadelake-Server
Update the stepping from 5 to 6, in order that the Cascadelake-Server CPU model can support AVX512VNNI and MSR based features exposed by ARCH_CAPABILITIES. Signed-off-by: Tao Xu <tao3.xu@intel.com> Message-Id: <20181227024304.12182-2-tao3.xu@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/i386/pc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 747548b..94ac9de 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -122,6 +122,7 @@ GlobalProperty pc_compat_3_1[] = {
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
+ { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
};
const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);