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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:52 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:52 +0100 |
| commit | acf949411ffb675edbfb707e235800b02e6a36f8 (patch) | |
| tree | ece985bec54622807e2847054c5eed67ec83ea52 /hw | |
| parent | 66787c7868d05d29974e09201611b718c976f955 (diff) | |
| download | qemu-acf949411ffb675edbfb707e235800b02e6a36f8.zip qemu-acf949411ffb675edbfb707e235800b02e6a36f8.tar.gz qemu-acf949411ffb675edbfb707e235800b02e6a36f8.tar.bz2 | |
target/arm: Make BASEPRI register banked for v8M
Make the BASEPRI register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new
AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to
be restricted).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c0dbbad..2a41e5d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -171,8 +171,8 @@ static inline int nvic_exec_prio(NVICState *s) running = -1; } else if (env->v7m.primask) { running = 0; - } else if (env->v7m.basepri > 0) { - running = env->v7m.basepri & nvic_gprio_mask(s); + } else if (env->v7m.basepri[env->v7m.secure] > 0) { + running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); } else { running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ } |