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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-12 10:33:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:19 +0100 |
| commit | a860df4f540d438a9531c70ff4eb0995841e7202 (patch) | |
| tree | 7c7a0a67d0c7bf593d54fd551bcf9a26a51bd27c /hw | |
| parent | 712bd17f3e6c5b33ad1e33661350164c9f8468bf (diff) | |
| download | qemu-a860df4f540d438a9531c70ff4eb0995841e7202.zip qemu-a860df4f540d438a9531c70ff4eb0995841e7202.tar.gz qemu-a860df4f540d438a9531c70ff4eb0995841e7202.tar.bz2 | |
hw/arm/mps2.c: Connect up armv7m clocks
Connect up the armv7m clocks on the mps2-an385/386/500/511.
Connect up the armv7m object's clocks on the MPS boards defined in
mps2.c. The documentation for these FPGA images doesn't specify what
systick reference clock is used (if any), so for the moment we
provide a 1MHz refclock, which will result in no behavioural change
from the current hardwired 1MHz clock implemented in
armv7m_systick.c:systick_scale().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-9-peter.maydell@linaro.org
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/mps2.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 81413b7..3671f49 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -86,6 +86,7 @@ struct MPS2MachineState { CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; Clock *sysclk; + Clock *refclk; }; #define TYPE_MPS2_MACHINE "mps2" @@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 25000000 +/* + * The Application Notes don't say anything about how the + * systick reference clock is configured. (Quite possibly + * they don't have one at all.) This 1MHz clock matches the + * pre-existing behaviour that used to be hardcoded in the + * armv7m_systick implementation. + */ +#define REFCLK_FRQ (1 * 1000 * 1000) + /* Initialize the auxiliary RAM region @mr and map it into * the memory map at @base. */ @@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine) mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->refclk = clock_new(OBJECT(machine), "REFCLK"); + clock_set_hz(mms->refclk, REFCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine) default: g_assert_not_reached(); } + qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); + qdev_connect_clock_in(armv7m, "refclk", mms->refclk); qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&mms->armv7m), "memory", |