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| author | Ed Tanous <etanous@nvidia.com> | 2025-07-03 07:42:46 -0700 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-03 17:36:45 +0200 |
| commit | 92096685a00414a813aa4735db1706e4e5c6917d (patch) | |
| tree | 12c4efc0e31ad62769d318b4324f715bdb78a4a7 /hw | |
| parent | 6888a4a9c8601005a2329fee6487c3c0df1348c0 (diff) | |
| download | qemu-92096685a00414a813aa4735db1706e4e5c6917d.zip qemu-92096685a00414a813aa4735db1706e4e5c6917d.tar.gz qemu-92096685a00414a813aa4735db1706e4e5c6917d.tar.bz2 | |
hw/arm/aspeed: Add second SPI chip to Aspeed model
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous <etanous@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/aspeed.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 9489750..8d7757e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init_flashes(&bmc->soc->spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_model, 1, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[1], + amc->spi2_model, 1, amc->num_cs2); } if (machine->kernel_filename && sc->num_cpus > 1) { |