diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-15 10:20:04 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-15 10:20:04 +0000 |
| commit | 81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f (patch) | |
| tree | 2bb4b8e5422dc39a98281abe7017003f5335a69c /hw | |
| parent | 0266c739abbed804deabb4ccde2aa449466ac3b4 (diff) | |
| parent | 0f8b09b22234460cb5b8766a25066cf6b5f06842 (diff) | |
| download | qemu-81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f.zip qemu-81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f.tar.gz qemu-81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190215' into staging
target-arm queue:
* gdbstub: Send a reply to the vKill packet
* Improve codegen for neon min/max and saturating arithmetic
* Fix a bug in clearing FPSCR exception status bits
* hw/arm/armsse: Fix miswiring of expansion IRQs
* hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
* MAINTAINERS: Remove Peter Crosthwaite from various entries
* arm: Allow system registers for KVM guests to be changed by QEMU code
* linux-user: support HWCAP_CPUID which exposes ID registers to user code
* Fix bug in 128-bit cmpxchg for BE Arm guests
* Implement (no-op) HACR_EL2
* Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
# gpg: Signature made Fri 15 Feb 2019 10:19:14 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190215: (25 commits)
gdbstub: Send a reply to the vKill packet.
target/arm: Add missing clear_tail calls
target/arm: Use vector operations for saturation
target/arm: Split out FPSCR.QC to a vector field
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
target/arm: Split out flags setting from vfp compares
target/arm: Fix arm_cpu_dump_state vs FPSCR
target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
target/arm: Remove neon min/max helpers
target/arm: Use tcg integer min/max primitives for neon
target/arm: Use vector minmax expanders for aarch32
target/arm: Use vector minmax expanders for aarch64
target/arm: Rely on optimization within tcg_gen_gvec_or
hw/arm/armsse: Fix miswiring of expansion IRQs
hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
MAINTAINERS: Remove Peter Crosthwaite from various entries
arm: Allow system registers for KVM guests to be changed by QEMU code
linux-user/elfload: enable HWCAP_CPUID for AArch64
target/arm: expose remaining CPUID registers as RAZ
target/arm: expose MPIDR_EL1 to userspace
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/armsse.c | 2 | ||||
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5d53071..9a8c495 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); for (j = 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, i + 32); + s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); } if (i == 0) { gpioname = g_strdup("EXP_IRQ"); diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 790a3d9..ab822f4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1841,7 +1841,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, } } break; - case 0xd18: /* System Handler Priority (SHPR1) */ + case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { val = 0; break; @@ -1956,7 +1956,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } nvic_irq_update(s); return MEMTX_OK; - case 0xd18: /* System Handler Priority (SHPR1) */ + case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { return MEMTX_OK; } |