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author | Peter Maydell <peter.maydell@linaro.org> | 2019-09-30 11:02:22 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-30 11:02:22 +0100 |
commit | 786d36ad416c6c199b18b78cc31eddfb784fe15d (patch) | |
tree | 5df78ee8c2a61247a609bfd25e0b3fcdaf2aa48e /hw | |
parent | 1e396381939bb7e4e799d9bf2a2af693954b5613 (diff) | |
parent | e4e34855e658b78ecac50a651cc847662ff02cfd (diff) | |
download | qemu-786d36ad416c6c199b18b78cc31eddfb784fe15d.zip qemu-786d36ad416c6c199b18b78cc31eddfb784fe15d.tar.gz qemu-786d36ad416c6c199b18b78cc31eddfb784fe15d.tar.bz2 |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190927' into staging
target-arm queue:
* Fix the CBAR register implementation for Cortex-A53,
Cortex-A57, Cortex-A72
* Fix direct booting of Linux kernels on emulated CPUs
which have an AArch32 EL3 (incorrect NSACR settings
meant they could not access the FPU)
* semihosting cleanup: do more work at translate time
and less work at runtime
# gpg: Signature made Fri 27 Sep 2019 15:32:43 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190927:
hw/arm/boot: Use the IEC binary prefix definitions
hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
tests/tcg: add linux-user semihosting smoke test for ARM
target/arm: remove run-time semihosting checks for linux-user
target/arm: remove run time semihosting checks
target/arm: handle A-profile semihosting at translate time
target/arm: handle M-profile semihosting at translate time
tests/tcg: clean-up some comments after the de-tangling
target/arm: fix CBAR register for AArch64 CPUs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# tests/tcg/arm/Makefile.target
Diffstat (limited to 'hw')
-rw-r--r-- | hw/arm/boot.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index bf97ef3..c264864 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -575,7 +575,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, goto fail; } - if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { + if (scells < 2 && binfo->ram_size >= 4 * GiB) { /* This is user error so deserves a friendlier error message * than the failure of setprop_sized_cells would provide */ @@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque) (cs != first_cpu || !info->secure_board_setup)) { /* Linux expects non-secure state */ env->cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + env->cp15.nsacr |= 3 << 10; } } @@ -1095,7 +1097,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, * we might still make a bad choice here. */ info->initrd_start = info->loader_start + - MIN(info->ram_size / 2, 128 * 1024 * 1024); + MIN(info->ram_size / 2, 128 * MiB); if (image_high_addr) { info->initrd_start = MAX(info->initrd_start, image_high_addr); } @@ -1155,13 +1157,13 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, * * Let's play safe and prealign it to 2MB to give us some space. */ - align = 2 * 1024 * 1024; + align = 2 * MiB; } else { /* * Some 32bit kernels will trash anything in the 4K page the * initrd ends in, so make sure the DTB isn't caught up in that. */ - align = 4096; + align = 4 * KiB; } /* Place the DTB after the initrd in memory with alignment. */ @@ -1178,7 +1180,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, info->loader_start + KERNEL_ARGS_ADDR; fixupcontext[FIXUP_ARGPTR_HI] = (info->loader_start + KERNEL_ARGS_ADDR) >> 32; - if (info->ram_size >= (1ULL << 32)) { + if (info->ram_size >= 4 * GiB) { error_report("RAM size must be less than 4GB to boot" " Linux kernel using ATAGS (try passing a device tree" " using -dtb)"); |