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authorAnthony Liguori <aliguori@us.ibm.com>2012-05-14 08:44:32 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-05-14 08:44:32 -0500
commit77f4c9a68aedb9b0d290a1def1bfc8714be862ec (patch)
tree1a216049e9f2b8bfe4acf250959ab204fab8cc57 /hw
parentd5c5dacc7027af2acfa87f860f11d7791776301f (diff)
parent94d1991445fa3582c042ee4e5b72606e2fc39cc2 (diff)
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Merge remote-tracking branch 'origin/master' into staging
* origin/master: sun4u: implement interrupt clearing registers sun4u: initialize OBIO interrupt mappings fix block loads broken in commit 30038fd818 Implement address masking for SPARC v9 CPUs vga: disable default VGA if appropriate -device is used cputlb: fix watchpoints handling
Diffstat (limited to 'hw')
-rw-r--r--hw/apb_pci.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 7e28808..c28411a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -85,6 +85,8 @@ typedef struct APBState {
unsigned int nr_resets;
} APBState;
+static void pci_apb_set_irq(void *opaque, int irq_num, int level);
+
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
@@ -113,6 +115,16 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
}
break;
+ case 0x1400 ... 0x143f: /* PCI interrupt clear */
+ if (addr & 4) {
+ pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
+ }
+ break;
+ case 0x1800 ... 0x1860: /* OBIO interrupt clear */
+ if (addr & 4) {
+ pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
+ }
+ break;
case 0x2000 ... 0x202f: /* PCI control */
s->pci_control[(addr & 0x3f) >> 2] = val;
break;
@@ -404,6 +416,9 @@ static void pci_pbm_reset(DeviceState *d)
for (i = 0; i < 8; i++) {
s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
}
+ for (i = 0; i < 32; i++) {
+ s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
+ }
if (s->nr_resets++ == 0) {
/* Power on reset */
@@ -426,6 +441,9 @@ static int pci_pbm_init_device(SysBusDevice *dev)
for (i = 0; i < 8; i++) {
s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
}
+ for (i = 0; i < 32; i++) {
+ s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
+ }
s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
/* apb_config */