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| author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
| commit | 707ea7ab4d55e0d907f72280eb2e4d376efeddf7 (patch) | |
| tree | 8d94dcbcd1ed3a2a4f3630b308e3218130d6c72c /hw | |
| parent | 34b0696be443e123d2d5225613c4604c66eb7a64 (diff) | |
| download | qemu-707ea7ab4d55e0d907f72280eb2e4d376efeddf7.zip qemu-707ea7ab4d55e0d907f72280eb2e4d376efeddf7.tar.gz qemu-707ea7ab4d55e0d907f72280eb2e4d376efeddf7.tar.bz2 | |
pnv/xive2: Introduce new capability bits
These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.
The 'XIVE exploitation mode' bit is a software bit that skiboot could
use to disable the XIVE OS interface and propose a P8 style XICS
interface instead. There are no plans for that for the moment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/pnv_xive2.c | 4 | ||||
| -rw-r--r-- | hw/intc/pnv_xive2_regs.h | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 1fa89c7..e220494 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1709,9 +1709,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = { }; /* - * POWER10 default capabilities: 0x2000120076f00000 + * POWER10 default capabilities: 0x2000120076f000FC */ -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000 +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC /* * POWER10 default configuration: 0x0030000033000000 diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index d45d17c..a46e513 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -31,6 +31,11 @@ #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) + /* XIVE2 Configuration */ #define X_CQ_XIVE_CFG 0x03 #define CQ_XIVE_CFG 0x018 |