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authorPeter Maydell <peter.maydell@linaro.org>2017-06-07 16:29:29 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-06-07 17:21:44 +0100
commit64175afc695c0672876fbbfc31b299c86d562cb4 (patch)
treec1d0c66fbfa5471767a2de6cdce1e0e1ab392d9e /hw
parentb55a69fe5f0a504dac6359bb7e99a72b130c3661 (diff)
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arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented
If EL3 is not implemented (ie only one security state) then the one and only ICC_BPR1 register behaves like the Non-secure ICC_BPR1 in an EL3-present configuration. In particular, its reset value is GIC_MIN_BPR_NS, not GIC_MIN_BPR. Correct the erroneous reset value; this fixes a problem where we might hit the assert added in commit a89ff39ee901. Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1496849369-30282-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw')
-rw-r--r--hw/intc/arm_gicv3_cpuif.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 09d8ba0..5cbafaf 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2039,11 +2039,7 @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
cs->icc_pmr_el1 = 0;
cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
- } else {
- cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
- }
+ cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |