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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-28 16:16:53 +0200 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-05-04 22:45:53 +0100 |
| commit | 5aa7f68a2df9604dbd7f95e9ecece6d553e46e32 (patch) | |
| tree | 32517c0578a6462e2358a62127bf5ef3c9172680 /hw | |
| parent | ef19ddfbf473d2e57239bfb160405cf9dd464cd1 (diff) | |
| download | qemu-5aa7f68a2df9604dbd7f95e9ecece6d553e46e32.zip qemu-5aa7f68a2df9604dbd7f95e9ecece6d553e46e32.tar.gz qemu-5aa7f68a2df9604dbd7f95e9ecece6d553e46e32.tar.bz2 | |
hw/sparc64: Fix code style for checkpatch.pl
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-4-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/sparc64/sparc64.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index cc0b9bd..fd29a79 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env) return; } cs = env_cpu(env); - /* check if TM or SM in SOFTINT are set - setting these also causes interrupt 14 */ + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { pil |= 1 << 14; } - /* The bit corresponding to psrpil is (1<< psrpil), the next bit - is (2 << psrpil). */ + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); |