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| author | Jim Shu <jim.shu@sifive.com> | 2022-10-03 04:14:39 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-10-14 14:29:50 +1000 |
| commit | 55144a1fd0d1f37b49ea051291decbbe427b7714 (patch) | |
| tree | 9843c9302248ba7960a9191c3b43a6a2c9912575 /hw | |
| parent | 07f4964d1785e9c230282074a5aef1eb7368d378 (diff) | |
| download | qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.zip qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.tar.gz qemu-55144a1fd0d1f37b49ea051291decbbe427b7714.tar.bz2 | |
hw/intc: sifive_plic: fix hard-coded max priority level
The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.
Also change interrupt priority register to use num_priorities Property
in maximum priority level.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/sifive_plic.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index af4ae36..f864efa 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; - plic->source_priority[irq] = value & 7; - sifive_plic_update(plic); + if (value <= plic->num_priorities) { + plic->source_priority[irq] = value; + sifive_plic_update(plic); + } } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) { qemu_log_mask(LOG_GUEST_ERROR, |