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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-10-12 13:09:45 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-09-13 20:10:49 +0200
commit50e4291d62970adaa1668aeb4e7dbc7c67739504 (patch)
tree20ce6f1760bf8ac9490afcd564b7f01fbf96feca /hw
parent13a07eb146c860f85f6fe665dd492f4f89146ba8 (diff)
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hw/pci-host/designware: Add 'host_mem' variable for clarity
designware_pcie_root_realize() uses get_system_memory() as the "host side memory region", as opposed to the "PCI side" one. Introduce the 'host_mem' variable for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20231012121857.31873-4-philmd@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/pci-host/designware.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 2bd467b..c3fc37b 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -395,6 +395,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
{
DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+ MemoryRegion *host_mem = get_system_memory();
MemoryRegion *address_space = &host->pci.memory;
PCIBridge *br = PCI_BRIDGE(dev);
DesignwarePCIEViewport *viewport;
@@ -435,7 +436,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
source = &host->pci.address_space_root;
- destination = get_system_memory();
+ destination = host_mem;
direction = "Inbound";
/*
@@ -460,7 +461,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
destination = &host->pci.memory;
direction = "Outbound";
- source = get_system_memory();
+ source = host_mem;
/*
* Configure MemoryRegion implementing CPU -> PCI memory