Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging

target/xtensa updates for 5.2:

- add NMI support;
- add DFPU option implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.

# gpg: Signature made Fri 21 Aug 2020 21:09:37 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200821-xtensa: (24 commits)
  target/xtensa: import DSP3400 core
  target/xtensa: import de233_fpu core
  tests/tcg/xtensa: add DFP0 arithmetic tests
  tests/tcg/xtensa: test double precision load/store
  tests/tcg/xtensa: add fp0 div and sqrt tests
  tests/tcg/xtensa: update test_lsc for DFPU
  tests/tcg/xtensa: update test_fp1 for DFPU
  tests/tcg/xtensa: update test_fp0_conv for DFPU
  tests/tcg/xtensa: expand madd tests
  tests/tcg/xtensa: update test_fp0_arith for DFPU
  tests/tcg/xtensa: fix test execution on ISS
  target/xtensa: implement FPU division and square root
  target/xtensa: add DFPU registers and opcodes
  target/xtensa: add DFPU option
  target/xtensa: don't access BR regfile directly
  target/xtensa: move FSR/FCR register accessors
  target/xtensa: rename FPU2000 translators and helpers
  target/xtensa: support copying registers up to 64 bits wide
  target/xtensa: add geometry to xtensa_get_regfile_by_name
  softfloat: add xtensa specialization for pickNaNMulAdd
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 5 insertions, 1 deletions

diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c
index edd53c9..1d5982a 100644
--- a/hw/xtensa/pic_cpu.c
+++ b/hw/xtensa/pic_cpu.c
@@ -35,9 +35,13 @@ void check_interrupts(CPUXtensaState *env)
 {
     CPUState *cs = env_cpu(env);
     int minlevel = xtensa_get_cintlevel(env);
-    uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
+    uint32_t int_set_enabled = env->sregs[INTSET] &
+        (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]);
     int level;
 
+    if (minlevel >= env->config->nmi_level) {
+        minlevel = env->config->nmi_level - 1;
+    }
     for (level = env->config->nlevel; level > minlevel; --level) {
         if (env->config->level_mask[level] & int_set_enabled) {
             env->pending_irq_level = level;