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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2014-05-05 21:39:38 -0700
committerStefan Hajnoczi <stefanha@redhat.com>2014-06-09 15:38:58 +0200
commit40e76f736d09535bc20e980a06c059229c7b5265 (patch)
treebace666bd3a8f317041baf2a9e6279d1f9080486 /hw
parent959e41473f2179850578482052fb73b913bc4e42 (diff)
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net: xilinx_ethlite: Fix Rx-pong interrupt
There is no CTRL_I bit in the pong buffer control register. The CTRL_I bit from the ping buffer masks both ping and pong buffers. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/net/xilinx_ethlite.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 5a434f6..1b177b3 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -196,8 +196,9 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
- if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
+ if (s->regs[R_RX_CTRL0] & CTRL_I) {
eth_pulse_irq(s);
+ }
/* If c_rx_pingpong was set flip buffers. */
s->rxbuf ^= s->c_rx_pingpong;