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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-07-09 13:41:31 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-07-18 10:40:27 +1000 |
| commit | 36a24df84a4728b1cd7425af24c0d30cd65a51b5 (patch) | |
| tree | 958079709a1af5633b4e5369843d3cca74531641 /hw | |
| parent | 2df778967b5d27c361c8f1389525d6c7e2dc9d10 (diff) | |
| download | qemu-36a24df84a4728b1cd7425af24c0d30cd65a51b5.zip qemu-36a24df84a4728b1cd7425af24c0d30cd65a51b5.tar.gz qemu-36a24df84a4728b1cd7425af24c0d30cd65a51b5.tar.bz2 | |
ppc: Fix support for odd MSR combinations
MacOS uses an architecturally illegal MSR combination that
seems nonetheless supported by 32-bit processors, which is
to have MSR[PR]=1 and one or more of MSR[DR/IR/EE]=0.
This adds support for it. To work properly we need to also
properly include support for PR=1,{I,D}R=0 to the MMU index
used by the qemu TLB.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions