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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-07-10 13:04:51 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:32 +0200 |
| commit | 3363277525958e173b4526f9dca225e125b1a5de (patch) | |
| tree | 58eb5fb7b67a6839480d710a9347e8402bf1101b /hw | |
| parent | 9a1f054d5bd9acaa82b66e09309482cba9eced63 (diff) | |
| download | qemu-3363277525958e173b4526f9dca225e125b1a5de.zip qemu-3363277525958e173b4526f9dca225e125b1a5de.tar.gz qemu-3363277525958e173b4526f9dca225e125b1a5de.tar.bz2 | |
target/riscv: fix shifts shamt value for rv128c
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions