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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-01-07 17:07:59 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-01-07 17:07:59 +0000 |
| commit | 257bb6501cda75e9ba0804cd5b45e17275928252 (patch) | |
| tree | 6bebe2b90e15867d8651da1f762d18ee650437e8 /hw | |
| parent | e07f844599525685db44ce74bf4ab12025d1d96a (diff) | |
| download | qemu-257bb6501cda75e9ba0804cd5b45e17275928252.zip qemu-257bb6501cda75e9ba0804cd5b45e17275928252.tar.gz qemu-257bb6501cda75e9ba0804cd5b45e17275928252.tar.bz2 | |
hw/intc/arm_gicv3_its: Correct comment about CTE RDBase field size
The comment says that in our CTE format the RDBase field is 36 bits;
in fact for us it is only 16 bits, because we use the RDBase format
where it specifies a 16-bit CPU number. The code already uses
RDBASE_PROCNUM_LENGTH (16) as the field width, so fix the comment
to match it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 6a3b145..14e8ef6 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -400,7 +400,7 @@ FIELD(DTE, ITTADDR, 6, 44) /* * 8 bytes Collection Table Entry size - * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE) + * Valid = 1 bit, RDBase = 16 bits */ #define GITS_CTE_SIZE (0x8ULL) #define GITS_CTE_RDBASE_PROCNUM_MASK MAKE_64BIT_MASK(1, RDBASE_PROCNUM_LENGTH) |