diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-22 20:16:13 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-22 20:16:13 +0000 |
| commit | 089af991182fb44915c30075ea4e202ad268afcb (patch) | |
| tree | 1319ba7583ed0135d670793832cdfe554805811a /hw | |
| parent | 3476562d361d641950d2b905b21824131dca5cf2 (diff) | |
| download | qemu-089af991182fb44915c30075ea4e202ad268afcb.zip qemu-089af991182fb44915c30075ea4e202ad268afcb.tar.gz qemu-089af991182fb44915c30075ea4e202ad268afcb.tar.bz2 | |
RTL8029 IDs support (Warner Losh)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1647 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ne2000.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/hw/ne2000.c b/hw/ne2000.c index 2b43ae4..2940abd 100644 --- a/hw/ne2000.c +++ b/hw/ne2000.c @@ -47,7 +47,9 @@ #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ +#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ +#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ #define EN0_RSR 0x0c /* rx status reg RD */ #define EN0_RXCR 0x0c /* RX configuration reg WR */ #define EN0_TXCR 0x0d /* TX configuration reg WR */ @@ -64,6 +66,11 @@ #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ +#define EN3_CONFIG0 0x33 +#define EN3_CONFIG1 0x34 +#define EN3_CONFIG2 0x35 +#define EN3_CONFIG3 0x36 + /* Register accessed at EN_CMD, the 8390 base addr. */ #define E8390_STOP 0x01 /* Stop and reset the chip */ #define E8390_START 0x02 /* Start the chip, clear reset */ @@ -447,6 +454,21 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) case EN2_STOPPG: ret = s->stop >> 8; break; + case EN0_RTL8029ID0: + ret = 0x50; + break; + case EN0_RTL8029ID1: + ret = 0x43; + break; + case EN3_CONFIG0: + ret = 0; /* 10baseT media */ + break; + case EN3_CONFIG2: + ret = 0x40; /* 10baseT active */ + break; + case EN3_CONFIG3: + ret = 0x40; /* Full duplex */ + break; default: ret = 0x00; break; |