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| author | Max Filippov <jcmvbkbc@gmail.com> | 2022-04-26 09:24:01 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-05-06 15:27:40 -0700 |
| commit | c6f3f334d157ff6b9bdc4e1b9d9874234138836a (patch) | |
| tree | ae4f9c8f07bab8bf6e9b034019bee9b661b0ced2 /hw/xtensa | |
| parent | 9e377be1f042e8618c54ee786d1022caa0e2409d (diff) | |
| download | qemu-c6f3f334d157ff6b9bdc4e1b9d9874234138836a.zip qemu-c6f3f334d157ff6b9bdc4e1b9d9874234138836a.tar.gz qemu-c6f3f334d157ff6b9bdc4e1b9d9874234138836a.tar.bz2 | |
hw/xtensa: fix reset value of MIROUT register of MX PIC
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'hw/xtensa')
| -rw-r--r-- | hw/xtensa/mx_pic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/xtensa/mx_pic.c b/hw/xtensa/mx_pic.c index d889f95..8211c99 100644 --- a/hw/xtensa/mx_pic.c +++ b/hw/xtensa/mx_pic.c @@ -334,7 +334,7 @@ void xtensa_mx_pic_reset(void *opaque) mx->miasg = 0; mx->mipipart = 0; for (i = 0; i < mx->n_irq; ++i) { - mx->mirout[i] = 1; + mx->mirout[i] = 0; } for (i = 0; i < mx->n_cpu; ++i) { mx->cpu[i].mipicause = 0; |